The present invention relates to a circuit for controlling a cache memory which is placed between a processor and a main memory, and particularly to a circuit for controlling a cache memory which is divided into a plurality of banks.
As disclosed in Japanese Laid-open Patent Publication No.3-257554, it has been a well-known technique to add a cache memory 3 to an electronic calculator or microprocessor along with a central processing unit 1 and a main memory 2, as shown in FIG. 8. The cache memory 3 is internally provided with a data memory 3a, tag memory 3b and hit detector 3c, so as to increase the processing speed by detecting and storing the most frequently accessed data in it.
Another well-known technique is a memory system disclosed in Japanese Laid-open Patent Publication No.2-90345, in which a bank register for storing expanded address information, which is needed to expand address space, is provided along with a cache memory so that the system uses both the main memory with bank function and the cache memory.
The performance of a microprocessor or the like with such a cache memory has been remarkably improved in recent years, and the capacity of the cache memory provided therein years, and the capacity of the cache memory provided therein has been increasing. The increase in cache capacity has been accompanied by the improvement of hit rate, so that the lowering of system performance due to external-bus access penalty has been drastically reduced. Instead, the lowering of system performance due to cache access penalty is causing problems.
Below, an embodiment of the control circuit for a cache memory which is divided into a plurality of banks so as to form so-called bank structure will be described with reference to the drawings.
FIG. 6 shows the structure of a conventional control circuit for a cache memory. An address signal ADD to be inputted is composed of a 7-bit index section ADDi and a 24-bit tag section ADDt. The cache memory is divided into two banks X and Y. The bank X is provided with a tag memory 11x and data memory 12x and the bank Y is provided with a tag memory 11y and data memory 12y. The banks X and Y are also provided with address comparators 13x and 13y, respectively, for comparing the index section ADDi of the address signal ADD with a reference address Mt from the tag memory 11x and for outputting an coincidence signal Sco when there is a coincidence between the two.
A clock is composed of a first-phase clock ph1 and second-phase ph2. The first-phase and second-phase clocks ph1 and ph2 have the same period and repeats the same cycle of Hi and Low, but compared to the cycle of the first-phase clock, the cycle of the second-phase clock is delayed by half the period. That is, each of the two clocks has the nega-tive-phase sequence with respect to the other. In the control circuit are provided a first-phase latch circuit L1h and second-phase latch circuit L2h which synchronize the signal with the first-phase clock ph1 and second-phase clock ph2, respectively. A write-access-hit-signal generating circuit 45 outputs, as a write-access-hit signal Swah, the logical product of a write-mode signal Swin for selectively instructing the writing or reading of data and a write instruction signal Swr, which will be described below. An enable-signal generating circuit 44 outputs, as an enable signal Sen, the logical product of the inverted write-access-hit signal Swah, which has been synchronized with the second-phase clock ph2 by the second-phase latch circuit L2, and the clock signal ph1. An address latch circuit 43 latches the index section ADDi of the address signal ADD and outputs it as a cache-access address ADDac.
On the output side of the above-mentioned banks X and Y is placed a hit-signal generating circuit 48 for outputting, as a hit signal Shit, the logical sum of the output Sco from the address comparator 13x, and the output Sco from the address comparator 13y, and a logical product calculator 49 for outputting, as the write instruction signal Swr, the logical product of the output Shit from the hit-signal generating circuit 48 and the inverted write-access-hit signal Swah mentioned above.
Each of the tag memories 11x and 11y is accessed by the cache-access address ADDac, so as to output the reference address Mt. Each of the data memories 12x and 12y is accessed by the cache-access address ADDac, so as to output read data.
The operation of the control circuit for a cache memory with the foregoing structure will be described below by using the timing chart in FIG. 7. Considering the delay time at the gate and the like, the waveforms of respective signals in FIG. 7 are drawn in deviation from the clocks ph1 and ph2. FIG. 7 shows the operations of the major signals when a hit that occurred in writing in the first bank X is sequentially followed by a read request, resulting in a hit in the second bank Y. It is observed from the drawing that the first-phase clock ph1 is Hi during the clock-cycle segments 1a, 2a, 3a, and 4a, while the second-phase clock ph2 is Hi during the clock-cycle segments 1b, 2b, 3b, and 4b. DATA is outputted from or inputted to the data memories 12x and 12y. FIG. 7 shows in descending order the states of the clocks ph1 and ph2, DATA, write-mode signal Swin (Hi indicates the write mode and Low indicates the read mode), write-access hit signal Swah, index section ADDi and tag section ADDt of the input address signal, cache-access address ADDac, and hit signal Shit.
First, the index section (Ai) of an address (A) is inputted as the input index section ADDi in the clock-cycle segment 1a, so as to be outputted as the cache access address ADDac in the clock-cycle segment 1b. Then, the reference address Mt is outputted from the tag memories 11x and 11y in response to the address (A), so as to be compared with the tag section (At) of the address (A) by the address comparators 13x and 13y. If both signals coincide as a result of comparison in the first bank X, the coincidence signal Sco is outputted in the clock-cycle segment 2a. With the coincidence signal Sco being outputted, the hit signal Shit is outputted and the write instruction signal Swr is outputted. Since the write-mode signal Swin is Hi during the clock-cycle segment 2a, the write-access hit signal Swah becomes Hi in the clock-cycle segment 2a, the address (A) is held as the cache-access address ADDac during the clock-cycle segments 2b and 3a, and the data is written in the data memory 12x during the clock-cycle segment 3a.
Subsequently, the write-access hit signal Swah becomes Low in the clock-cycle segment 3a. When the index section (Bi) of an address (B) is outputted as the cache-access address ADDac in the clock-cycle segment 3a, the reference address Mt is outputted from the tag memories 11x and 11y in of response, so as to be compared with the tag section (Bt) the address (B). If both signals coincide as a result of comparison in the second bank Y, the coincidence signal Sco is outputted in the clock-cycle segment 4a, so as to output the hit signal Shit. However, the structure described above is disadvantageous in that two cycles are required to carry out the writing of data in the cache memory, for the presence or absence of a cache hit is determined in the first cycle and then data is written in the cache memory in the second cycle.
There is still another technique as disclosed in Japanese Laid-open Patent No.2-156351, in which the data memory is placed between the central processing unit and main memory of an electronic calculator so that the address in the main memory of the data, which has been stored in the data memory, is stored in the tag memory. When processor address data is outputted from the central processing unit, address data, which was outputted from the tag memory in response to the processor address memory, is compared with the processor address memory to determine whether there was a hit or miss. By further providing a circuit for converting the address and a circuit for switching the address so that the processor address data is fetched to be outputted in reading data and that the processor address data is delayed by specified cycles in writing data, the reading of data is carried out simultaneously with the writing of data. However, since the conversion of the address number requires other subsequent procedures, the processing speed is not increased.
The object of the present invention, which was conducted in order to solve the above-mentioned problems, is to constitute a circuit for controlling a cache memory which enables the writing of data in consecutive cycles so as to increase the processing speed.